Reference is made to FIG. 1 showing a circuit diagram of a conventional negative charge pump circuit 10. The circuit 10 includes a first CMOS switching circuit 12 and a second CMOS switching circuit 14. Each switching circuit 12 and 14 is formed by a series-connected pair of MOSFETs (drive transistors) including a p-channel transistor 16 and an n-channel transistor 18. The first CMOS switching circuit 12 is connected between a positive voltage supply node Vpos and a ground reference node Vgnd (with the source of transistor 16 connected to the positive voltage supply node Vpos and the source of transistor 18 connected to the ground reference node Vgnd). The second CMOS switching circuit 14 is connected between the ground reference node Vgnd and a negative voltage output node Vneg (with the source of transistor 16 connected to the ground reference node Vgnd and the source of transistor 18 connected to the negative voltage output node Vneg). The transistors 16 and 18 have their source-drain paths connected to each other at the drain terminals of the transistors 16, 18 to define a positive node 20 for the first CMOS switching circuit 12 and a negative node 22 for the second CMOS switching circuit 14. A fly capacitor Cfly is connected between the positive and negative nodes 20 and 22, respectively. An output capacitor Cout is connected between the negative voltage output node Vneg and the ground reference node Vgnd. The gate terminals of the drive transistors within the first and second CMOS switching circuits 12 and 14 are each driven by a driver circuit 24 in response to a clock signal (clk1-clk4) generated by a non-overlap clock generator circuit 26. FIG. 2 illustrates the general shape for the waveform of the clock signals clk1-clk4. During a first phase 40 of each cycle 42 of the waveform, the p-channel transistors 16 in the first and second CMOS switching circuits 12 and 14 are each turned on and current flows from the positive voltage supply node Vpos to the ground reference node Vgnd to charge the capacitor Cfly. During a second phase 44 of cycle 42, the n-channel transistors 18 in the first and second CMOS switching circuits 12 and 14 are each turned on connecting the more positive plate of the charged capacitor Cfly to ground and the more negative plate of the charged capacitor Cfly to the negative voltage output node Vneg. A negative voltage is eventually generated at the negative voltage output node Vneg having an absolute value equal to the voltage at the positive voltage supply node Vpos.
The control of the charge pump circuit 10 is preferably open loop for reasons of simplicity and cost reduction. Thus, soft start control over charge pump circuit operation is typically not used. The duty cycle of the clock signals clk1-clk4 is fixed. There is a need in the art, however, for soft start control of an open loop-type charge pump circuit.